Exemplary embodiments relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a non-volatile memory device having a 3-dimensional (3-D) structure (hereinafter simply referred to as a ‘3-D non-volatile memory device’) and a method of manufacturing the same.
A non-volatile memory device retains data although the supply of power is stopped. As memory devices having a 2-dimensional (2-D) structure in which memory cells are fabricated on a silicon substrate in the form of a single layer have reached the limit in increasing the degree of integration, there is proposed a 3-D non-volatile memory device in which memory cells are vertically stacked on a silicon substrate.
The structure and features of the known 3-D non-volatile memory device are described below with reference to relevant drawings.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional method of manufacturing a 3-D non-volatile memory device. It is to be noted that only part of one of strings is shown in the drawings, for the description purpose. In other words, only a plurality of memory cells and one selection transistor stacked along a channel protruded from a substrate are shown.
As shown in FIG. 1A, a plurality of interlayer insulating layers 11 and a plurality of sacrificial layers (not shown) are alternately stacked over a substrate 10 and are then etched to form a trench. The plurality of sacrificial layers is formed to secure regions where a plurality of word lines and a plurality of selection gate lines will be formed in subsequent processes. In general, since the selection gate line has a longer length than the word line, the sacrificial layer for securing the selection gate line regions is thicker than the sacrificial layer for securing the word line regions.
A channel 12 is formed in the trench. The plurality of interlayer insulating layers 11 and the plurality of sacrificial layers are etched to form a slit between the adjacent channels 12.
A plurality of word line regions and a plurality of selection gate line regions are formed by removing the plurality of sacrificial layers exposed through the inner wall of the slit. Here, the selection gate line region D1 is thicker than the word line region D2.
A conductive layer 13 is formed on the entire surface of the resulting structure in which the plurality of word line regions and the plurality of selection gate line regions are formed. Here, the plurality of word line regions is fully filled with the conductive layer 13, whereas the plurality of selection gate line regions is partially filled with the conductive layer 13.
As shown in FIG. 1B, the conductive layer 13 formed on the inner wall of the slit is etched in order to separate a plurality of word lines 13A and a plurality of selection gate lines from each other. In this process, however, the conductive layer 13 formed in the plurality of selection gate line regions may be fully removed (reference numeral ‘A’).
In general, since the selection transistors of a non-volatile memory device have higher threshold voltages than memory cells, the threshold voltages of the selection transistors are to be controlled by controlling the impurity doping concentration of a channel. A conventional method of manufacturing a 3-D non-volatile memory device, however, may have difficulty in controlling the threshold voltages of the selection transistors because the channel is filled in the trench.